Systems and methods for Stretching Clock Cycles in the Internal Clock Signal of a Memory Array Macro

A method for generating an internal clock signal in a memory array macro comprising:

• receiving a regular periodic external clock signal at an input of a local clock buffer for a memory array macro;
• and
• providing an internal clock signal at an output of the local clock buffer;
• wherein for a clock cycle of the external clock signal during which the memory array macro is accessed, a corresponding clock cycle of the internal clock signal is generated, wherein a first half-period of the clock cycle of the internal clock signal is greater than a half-period of the external clock signal, and wherein a second half-period is greater than the half-period of the external clock signal.

A memory system comprising:

• an external clock source configured to generate an external clock signal;
• and
• a plurality of memory array macros configured to receive the external clock signal;
• wherein each memory array macro includes a local clock buffer that generates an internal clock signal during a memory access to the memory array macro, wherein a clock cycle of the internal clock signal has a first half-period that is greater than a corresponding first half-period of a clock cycle of the external clock signal;
• wherein the clock cycle of the internal clock signal has a second half-period that is greater than a corresponding second half-period of the clock cycle of the external clock signal;
• and
• wherein each local clock buffer includes a first set of components that form a first signal path and a second set of components that form a second signal path, wherein the first signal path includes one or more faster-than-nominal components, and wherein the second signal path includes a delay element.