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US 2010/0302844 A1Published application
Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling
AssigneeMicron Technology, Inc.
InventorsHagop A. Nazarian, Aaron Yip
Life of this patent
Estimating the term…
Abstract
A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The shift of the floating gates decreases the floating gate to floating gate coupling.
Claims10
1-21. (canceled)
A non-volatile memory device comprising:
- an array of non-volatile memory cells, each memory cell comprising a charge storage structure;
- a plurality of bit lines each connected to a plurality of memory cells in a string,
- a plurality of word lines each connected to a plurality of memory cells, wherein side walls of the charge storage structure of a first memory cell in a string are not vertically aligned with side wall the charge storage structure of an adjacent memory cell in the string.
The non-volatile memory device of claim 26, wherein the plurality of bit lines are nonlinear.
A non-volatile memory device comprising:
- an array of non-volatile memory cells, each memory cell comprising a charge storage structure;
- a plurality of bit lines each connected to a plurality of memory cells in a string,
- a plurality of word lines each connected to a plurality of memory cells, wherein side walls of each charge storage structure connected to a first word line are not horizontally aligned with side walls of each charge storage structure of each memory cell connected to a second word line, the first and second word lines being adjacent one another.
Dependencies are inferred from the claim text.