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US 2010/0301393 A1Published application
Field effect transistor and manufacturing method therefor
OwnerNobuaki TERAGUCHIinventor
Life of this patent
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Abstract
There is provided a field effect transistor of a normally-OFF operation having a low contact resistance and capable of avoiding increases in on-resistance and maintaining high channel mobility. In this field effect transistor, a thin-layer portion 6a of an AlGaN barrier layer 6, which is formed on V defects 13 of a second GaN layer 4 and on non-grown regions G1 of a third GaN layer 5 adjoining the V defects 13, can be made thinner than a flat portion 6b without etching. Therefore, increases in the on-resistance can be avoided without causing degradation of the channel mobility due to etching damage.
Claims20
A field effect transistor comprising:
- a substrate having surface-processed portions formed at predetermined places in a surface thereof;
- a buffer layer formed on the substrate;
- a first nitride-based group III-V compound semiconductor layer which is formed on the buffer layer and which has dislocations generated at places corresponding to the surface-processed portions but has no V defects that are V-shaped non-grown regions whose nuclei are given by the dislocations;
- a second nitride-based group III-V compound semiconductor layer formed on the first nitride-based group III-V compound semiconductor layer and having V defects that are V-shaped non-grown regions whose nuclei are given by the dislocations;
- a third nitride-based group III-V compound semiconductor layer which is formed on the second nitride-based group III-V compound semiconductor layer so that the V defects are not buried thereby and which has non-grown regions adjacent to the V defects but has no additional V defects other than the V defects;
- and
- a fourth nitride-based group III-V compound semiconductor layer which is formed on the third nitride-based group III-V compound semiconductor layer and which has a thin-layer portion formed along the V defects and the non-grown regions adjacent to the V defects, and a flat portion adjoining the thin-layer portion and formed outside the V defects and being thicker than the thin-layer portion, wherein
- the first to third nitride-based group III-V compound semiconductor layers constitute a channel layer, the fourth nitride-based group III-V compound semiconductor layer constitutes a barrier layer, and the third nitride-based group III-V compound semiconductor layer and the fourth nitride-based group III-V compound semiconductor layer constitute a heterojunction.
5 more elements
A field effect transistor manufacturing method comprising the steps of:
- forming a mask pattern on a substrate with resist or a material having etching-resistant property;
- forming protrusive surface-processed portions at predetermined portions of the substrate by etching portions out of the substrate that are not covered with the mask pattern;
- subsequently forming a buffer layer on the substrate;
- making growth of a first nitride-based group III-V compound semiconductor layer that constitutes a channel layer on the buffer layer under such a growth temperature condition that dislocations are generated from places corresponding to the protrusive surface-processed portions while V defects that are V-shaped non-grown regions whose nuclei are given by the dislocations are not generated;
- making growth of a second nitride-based group III-V compound semiconductor layer to constitute a channel layer under such a growth temperature condition that the V defects are generated on the first nitride-based group III-V compound semiconductor layer;
- making growth of a third nitride-based group III-V compound semiconductor layer to constitute a channel layer on the second nitride-based group III-V compound semiconductor layer under such a growth temperature condition that the V defects of the second nitride-based group III-V compound semiconductor layer are not buried while non-grown regions adjacent to the V defects are generated but additional V defects other than the V defects are not generated;
- and
- forming, on the third nitride-based group III-V compound semiconductor layer, a fourth nitride-based group III-V compound semiconductor layer which becomes a barrier layer having a thin-layer portion formed along the V defects and the non-grown regions adjacent to the V defects, and a flat portion adjoining the thin-layer portion and formed outside the V defects and being thicker than the thin-layer portion, and which constitutes a heterojunction in combination with the third nitride-based group III-V compound semiconductor layer.
5 more elements
A field effect transistor manufacturing method comprising the steps of:
- patterning a mask material for selective growth on a substrate to form surface-processed portions of the patterned mask material at predetermined places on the substrate;
- subsequently forming a buffer layer on the substrate;
- making growth of a first nitride-based group III-V compound semiconductor layer that constitutes a channel layer on the buffer layer under such a growth temperature condition that dislocations are generated from places corresponding to the surface-processed portions while V defects that are V-shaped non-grown regions whose nuclei are given by the dislocations are not generated;
- making growth of a second nitride-based group III-V compound semiconductor layer to constitute a channel layer on the first nitride-based group III-V compound semiconductor layer under such a growth temperature condition that the V defects are generated;
- making growth of a third nitride-based group III-V compound semiconductor layer to constitute a channel layer on the second nitride-based group III-V compound semiconductor layer under such a growth temperature condition that the V defects generated in the second nitride-based group III-V compound semiconductor layer are not buried while non-grown regions adjacent to the V defects are generated but additional V defects other than the V defects are not generated;
- and
- forming, on the third nitride-based group III-V compound semiconductor layer, a fourth nitride-based group III-V compound semiconductor layer which becomes a barrier layer having a thin-layer portion formed along the V defects and the non-grown regions adjacent to the V defects, and a flat portion adjoining the thin-layer portion and formed outside the V defects and being thicker than the thin-layer portion, and which constitutes a heterojunction in combination with the third nitride-based group III-V compound semiconductor layer.
4 more elements
Dependencies are inferred from the claim text.