US 2010/0301386 A1Published application

Integrated structure of igbt and diode and method of forming the same

AssigneeAnpec Electronics Corporation

InventorsWei-Chieh Lin, Ho-Tai Chen, Jen-Hao Yeh, Li-Cheng Lin, Shih-Chieh Hung

Life of this patent

Estimating the term…

Loading patent…

Abstract

An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Claims19

Dependent claims

An integrated structure of an insulated gate bipolar transistor (IGBT) and a diode, comprising:

a first conductive layer;
a semiconductor substrate of a first conductivity type disposed on the first conductive layer and electrically connected to the first conductive layer, wherein the semiconductor substrate serves as a collector of the IGBT;
a plurality of doped cathode regions of a second conductivity type, wherein each of the doped cathode regions has a different doped area, the doped cathode regions are arranged in a hierarchy order with the doped cathode region having a larger doped area disposed atop the doped cathode region having a smaller doped area, the doped cathode regions are in contact with and electrically connected to each other, and the doped cathode regions are electrically connected to the first conductive layer;
a drift epitaxial layer of the second conductivity type disposed on the semiconductor substrate;
at least a gate electrode disposed on the drift epitaxial layer;
at least a gate insulating layer disposed between the drift epitaxial layer and the gate electrode;
a doped base region of the first conductivity type disposed on the drift epitaxial layer and adjacently connected to the gate insulating layer;
a doped source region of the second conductivity type disposed on the doped base region and adjacently connected to the gate insulating layer;
a doped contact region of the first conductivity type disposed on the doped base region;
and
a second conductive layer disposed on the doped base region and electrically connected to the doped source region and the doped contact region.

8 more elements

A fabrication method for forming an integrated structure of an insulated gate bipolar transistor (IGBT) and a diode, the fabrication method comprising the steps of:

providing a semiconductor substrate, the semiconductor substrate having a first conductivity type, and the semiconductor substrate comprising an upper surface and a lower surface;
forming at least a first doped cathode region and at least a second doped cathode region in the semiconductor substrate, the first doped cathode region and second doped cathode region having a second conductivity type, and the first doped cathode region and second doped cathode region overlapping and contacting with each other, wherein a depth of the second doped cathode region is shallower than a depth of the first doped cathode region, and an implanted area of the second doped cathode region is larger than an implanted area of the first doped cathode region;
forming a drift epitaxial layer on the upper surface of the semiconductor substrate, the drift epitaxial layer having the second conductivity type;
forming at least a gate insulating layer and at least a gate electrode on the drift epitaxial layer, the gate insulating layer being disposed between the drift epitaxial layer and the gate electrode;
forming a doped base region in the drift epitaxial layer, the doped base region having the first conductivity type and being adjacently connected to the gate insulating layer;
forming a doped source region in the doped base region, the doped source region having the second conductivity type and being adjacently connected to the gate insulating layer;
forming a doped contact region in the doped base region, the doped contact region having the first conductivity type;
forming a first conductive layer on the doped base region, the first conductive layer being electrically connected to the doped source region and the doped contact region;
performing a thinning process on the lower surface of the semiconductor substrate until the first doped cathode region is exposed;
and
forming a second conductive layer on the lower surface of the semiconductor substrate, the second conductive layer being electrically connected to the first doped cathode region and the semiconductor substrate.

8 more elements

Dependencies are inferred from the claim text.