Body contact structure for in-line voltage contrast detection of pfet silicide encroachment
AssigneeInternational Business Machines Corporation
InventorsOliver D. Patterson, Ishtiaq Ahsan
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Abstract
Test structures for in-line voltage contrast detection of PFET silicide encroachment defects are disclosed. Embodiments of the present invention provide for improved PFET test structures for detecting encroachment defects using VC imaging techniques. The test structures use body contacts, and the PFET components (source, drain, body, and gate) are either grounded, or floating, depending on the configuration. Some embodiments of the present invention also enable the use of positive mode conditions with PFET test structures, which provides for improved contrast in the VC images, improving the effectiveness of the defect detection achieved with VC imaging.
Claims20
A semiconductor test structure comprising:
- a PFET transistor, the PFET transistor comprising a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact, wherein the source region and drain region are floating, and wherein the body contact is electrically connected to the body of the PFET transistor, and wherein the body contact is electrically connected to ground, thereby grounding the body of the PFET transistor.
A semiconductor test structure comprising:
- a PFET transistor, the PFET transistor comprising a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact, wherein the body contact is electrically connected to the body of the PFET transistor, and wherein the body contact is electrically connected to a sense pad, thereby electrically connecting the body of the PFET transistor to the sense pad, and wherein the drain region is electrically connected to ground.
A semiconductor test structure comprising:
- a PFET transistor, the PFET transistor comprising a source region, a drain region, a gate disposed between the source region and the drain region, and a body disposed under the gate, wherein the wherein the source region is electrically connected to the gate of the PFET transistor, and wherein the drain region is electrically connected to ground.
Dependencies are inferred from the claim text.