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US 2010/0250849 A1Published application
Hierarchical memory architecture to connect mass storage devices
AssigneeMicron Technology, Inc.
InventorSean Eilert
Life of this patent
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Abstract
A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.
Claims20
A hierarchical memory system coupled to a processor through a processor frontside bus, comprising:
- a concentrator device having a frontside bus port connected to the processor frontside bus and a backside port, where data stored in memory devices external to the backside port is received and stored in PCM arrays and transferred to the processor through the frontside bus port.
A hierarchical memory structure to provide storage for a processor, comprising:
- a first concentrator device having a frontside bus port to couple to the processor and a backside port;
- and
- a second concentrator device having a frontside bus port coupled to the backside port of the first concentrator device and a backside port to couple external memory devices.
A hierarchical memory system, comprising:
- a concentrator device having a frontside bus port to connect to a processor frontside bus and a backside port, where data stored in memory devices external to the backside port is received and stored in Phase Change Memory (PCM) arrays and corrected by an Error-Correcting Code (ECC) Engine block before transfer to a processor through the frontside bus port.
A hierarchical memory storage, comprising:
- a concentrator device to couple a frontside bus port to a processor and a backside port to external storage devices, wherein the concentrator device includes Phase Change Memory (PCM) arrays to store data and Error-Correcting Code (ECC) to correct data transferred between the processor and the external storage devices.
Dependencies are inferred from the claim text.