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US 2010/0250828 A1Published application
Control signal output pin to indicate memory interface control flow
OwnerBrent Ahlquistinventor
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Abstract
Embodiments include but are not limited to apparatuses and systems including a memory array including a plurality of non-volatile memory cells, and a control signal output pin operatively coupled to the memory array. The control signal output pin may be configured to provide a control signal indicative of the memory interface control flow including, for example, an availability of the memory array for reading or writing. Other embodiments may be described and claimed.
Claims20
An apparatus comprising:
- a memory array including a plurality of non-volatile memory cells;
- and
- a control signal output pin operatively coupled to the memory array and configured to provide a control signal indicative of an availability of the memory array for reading or writing.
A system comprising:
- a memory apparatus including:
- a plurality of non-volatile memory cells;
- and
- a control signal output pin operatively coupled to the plurality of memory cells and configured to provide a control signal indicative of a control signal output pin operatively coupled to the memory array and configured to provide a control signal indicative of an availability of the memory array for reading or writing;
- a memory controller operatively coupled to the memory apparatus and configured to determine whether the control signal indicates the availability of the memory array for reading or the availability of the memory array for writing based at least in part on an operation being performed by the memory apparatus;
- a host logic device bus operatively coupled between the memory apparatus and the memory controller;
- and
- a bus interface unit operatively coupled between the memory apparatus and the host logic device bus.
5 more elements
A method comprising:
- providing a memory apparatus including a memory array having a plurality of non-volatile memory cells;
- and
- asserting a control signal to indicate an availability of the memory array for reading or writing.
Dependencies are inferred from the claim text.