Hierarchical memory architecture using a concentrator device
AssigneeMicron Technology, Inc.
InventorSean Eilert
Life of this patent
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Abstract
A hierarchical memory storage using a concentrator device that is located between a processor and memory devices. The concentrator device includes a page buffer, a Phase-Change Memory (PCM) memory array, and a configurable Error-Correcting Code (ECC) engine to accommodate temporary storage for data transfers between the processor and the memory devices.
Claims20
A concentrator device having a frontside port to couple to a processor and provide hierarchical storage to memory devices coupled to a backside port, where data received from the backside port is cached in a Phase-Change Memory (PCM).
A concentrator device to separate external memory devices from a processor, comprising:
- a frontside bus port to receive data from the processor and a backside port coupled to the external memory devices;
- a PCM memory array;
- a page buffer to store the data received from the processor for programming into the PCM memory array;
- and
- a command queue for issuing memory commands.
A concentrator device to couple external memory devices to a processor, comprising:
- a page buffer to hold data received from the processor;
- a Phase-Change Memory (PCM) memory array to store the data transferred from the page buffer;
- and
- a configurable Error-Correcting Code (ECC) engine to provide error detection and correction for the data written to the PCM memory array, where the page buffer, PCM and ECC engine in the concentrator device accommodate temporary storage for data transfers between the processor and the external memory devices.
Dependencies are inferred from the claim text.