Method for making a stressed non-volatile memory device
AssigneeFreescale Semiconductor, Inc.
InventorsKonstantin V. Loiko, Brian A. Winstead, Taras A. Kirichenko
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Abstract
A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer.
Claims20
A method of making a semiconductor device on a semiconductor layer, comprising:
- forming a gate dielectric over the semiconductor layer;
- forming a layer of gate material over the gate dielectric;
- etching the layer of gate material to form a select gate;
- forming a storage layer that extends over the select gate and over a portion of the semiconductor layer;
- depositing an amorphous silicon layer over the storage layer;
- etching the amorphous silicon layer to form a control gate;
- and
- annealing the semiconductor device to crystallize the amorphous silicon layer.
A method of making a semiconductor device on a semiconductor layer, comprising:
- forming a gate dielectric over the semiconductor layer;
- forming a layer of gate material over the gate dielectric;
- etching the layer of gate material to form a select gate;
- forming a charge storage layer that extends over the select gate and over a portion of the semiconductor layer;
- depositing an amorphous silicon layer over the charge storage layer;
- etching the amorphous silicon layer to form a control gate;
- forming a liner on the semiconductor device;
- forming a capping layer over the liner;
- and
- annealing the semiconductor device to crystallize the amorphous silicon layer.
A method of making a semiconductor device on a semiconductor layer, comprising:
- forming a gate dielectric over the semiconductor layer;
- forming a polysilicon layer over the gate dielectric;
- etching the polysilicon layer to form a select gate;
- forming a charge storage layer that extends over the select gate and over a portion of the semiconductor layer, wherein the charge storage layer comprises nanocrystals;
- depositing an amorphous silicon layer over the charge storage layer;
- etching the amorphous silicon layer to form a control gate, the control gate having a portion formed over a portion of the select gate;
- forming an insulating liner on the semiconductor device;
- forming a tensile stressed silicon nitride layer over the insulating liner;
- annealing the semiconductor device to crystallize the amorphous silicon layer;
- and
- removing the tensile stressed silicon nitride layer.
Dependencies are inferred from the claim text.