Pipe latch circuit and semiconductor memory device using the same
AssigneeHynix Semiconductor Inc.
InventorsYouk Hee Kim, Bok Rim Ko, Young Joo Kim
Life of this patent
Estimating the term…
Abstract
A pipe latch circuit comprises a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all data are outputted to an outside upon read operation, an input/output control signal generating unit which generates a plurality of input control signals and output control signals in response to a read strobe signal and a clock signal, and is reset in response to the reset signal, and a pipe latch unit which latches inputted data in response to the input control signals and outputs the latched data in response to the output control signals.
Claims21
A pipe latch circuit, comprising:
- a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all of data are outputted to an outside upon a read operation;
- an input/output control signal generating unit which generates a plurality of input control signals and output control signals in response to a read strobe signal and a clock signal, and is reset in response to the reset signal;
- and
- a pipe latch unit which latches inputted data in response to the input control signals and outputs the latched data in response to the output control signals.
A semiconductor memory device, comprising:
- a read period signal generating unit which receives a read pulse, a clock signal and a burst signal and generates a read period signal, the read period signal being enabled upon entry into a read operation and disabled after all of data are outputted to an outside;
- and
- a pipe latch circuit which controls input/output of the data in response to a read strobe signal and the clock signal and is initialized when the read period signal is disabled or upon entry into a write operation.
Dependencies are inferred from the claim text.