Pipe latch circuit and semiconductor memory device using the same

Abstract

A pipe latch circuit comprises a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all data are outputted to an outside upon read operation, an input/output control signal generating unit which generates a plurality of input control signals and output control signals in response to a read strobe signal and a clock signal, and is reset in response to the reset signal, and a pipe latch unit which latches inputted data in response to the input control signals and outputs the latched data in response to the output control signals.

Dependencies are inferred from the claim text.