Method for mitigating imprint in a ferroelectric memory

An array of ferroelectric memory cells that allows imprint mitigation comprising:

• a plurality of ferroelectric memory cells respectively coupled to a plurality of word lines, plate lines, and bit lines;
• a word line driver for driving the word lines;
• a plate line driver for driving the plate lines;
• a bit line driver for driving the bit lines;
• and
• an isolation device driver for driving a plurality of isolation devices coupled to a plurality of bit lines.

A method for mitigating imprint in an array of ferroelectric memory cells including a plurality of word lines, plate lines, and bit lines, the method comprising:

• switching a group of memory cells in the array from an original data state to a first polarization state;
• store the original polarization state in the respective sense amplifiers;
• switching the group of memory cells in the array from the first polarization state to a second polarization state that is opposite the first polarization state;
• and
• switching the group of memory cells in the array from a second polarization state to a restored original data state.

A ferroelectric memory array comprising:

• a plurality of 1T/1C ferroelectric memory cells each having a bit line node, a plate line node, and a word line node;
• a plurality of sense amplifiers coupled to the bit line nodes of the memory cells through a plurality of isolation devices;
• and
• a plurality of bit line isolation devices coupled between the bit line nodes of the memory cells.