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US 2010/0246079 A1Published application
Power supply clamp circuit
AssigneeFujitsu Microelectronics Limited
InventorTeruo SUZUKI
Life of this patent
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Abstract
A power supply clamp circuit includes a first transistor including a metal silicide layer that is formed in a substrate between a first electrode coupling part in a first drain region and a first gate electrode, and a second transistor including a first metal silicide layer and a second metal silicide layer each of which is formed in a substrate between a second electrode coupling part in a second drain region and a second gate electrode, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other.
Claims10
A power supply clamp circuit comprising:
- a first transistor including a metal silicide layer that is formed in a substrate between a first electrode coupling part in a first drain region and a first gate electrode;
- and
- a second transistor including a first metal silicide layer and a second metal silicide layer each of which is formed in a substrate between a second electrode coupling part in a second drain region and a second gate electrode,
- wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other.
1 more element
Dependencies are inferred from the claim text.