US 2010/0246076 A1 · Electrical Overstress Protection Circuit

Abstract

A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.

Claims25

Dependent claims

A semiconductor circuit comprising:

a network of a resistor and a capacitor located between a power supply node and electrical ground;
an inverter comprising an output node at a serial connection of a drain of a p-type field effect transistor and a drain of an n-type transistor connection and an input node at a parallel connection of a gate of said p-type field effect transistor and a gate of said n-type transistor;
a discharge transistor connected between said power supply node and electrical ground, wherein said output node of said inverter is electrically connected to a gate of said discharge transistor;
and
an electronic component having voltage snapback property or diodic property, wherein a first end of said electronic component is connected to said power supply node or electrical ground, and wherein a second end of said electronic component is connected to said input node of said inverter or said output node of said inverter.

2 more elements

A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design for a semiconductor structure, said design structure comprising:

a first data representing a network of a resistor and a capacitor located between a power supply node and electrical ground;
a second data representing an inverter which comprises an output node at a serial connection of a drain of a p-type field effect transistor and a drain of an n-type transistor connection and an input node at a parallel connection of a gate of said p-type field effect transistor and a gate of said n-type transistor;
a third data representing a discharge transistor connected between said power supply node and electrical ground, wherein said output node of said inverter is electrically connected to a gate of said discharge transistor;
and
a fourth data representing an electronic component having voltage snapback property or diodic property, wherein a first end of said electronic component is connected to said power supply node or electrical ground, and wherein a second end of said electronic component is connected to said input node of said inverter or said output node of said inverter.

2 more elements

Dependencies are inferred from the claim text.

Electrical Overstress Protection Circuit

Life of this patent

Electrical Overstress Protection Circuit

Life of this patent

Abstract

Claims25