US 2010/0245300 A1 · Shift Register

Abstract

A shift register including a plurality of multi-stage shift register circuits is provided. The mth stage shift register circuit includes a node, a shift register unit and a control circuit. A first control signal, enabled in an mth period, is defined on the node. The shift register unit is controlled by an (m−1)th stage output signal provided by an (m−1)th stage shift register circuit and a clock signal for providing the enabled mth stage output signal in the mth period, and controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing a disenabled mth stage output signal in the (m+1)th period. The control circuit, controlled by the clock signal, provides and outputs an mth stage second control signal to the (m−1)th stage shift register circuit according to the mth stage first control signal, wherein m is a natural number greater than 1.

Claims19

Dependent claims

A shift register comprises a plurality of multi-stage shift register circuits respectively used for outputting a plurality of shift output signals, wherein an mth stage shift register circuit of the multi-stage shift register circuits comprises:

an mth stage first node, wherein an mth stage first control signal enabled in an mth period is defined on the mth stage first node;
an mth stage shift register unit controlled by an (m−1)th stage output signal, which is enabled in an (m−1)th period and provided by an (m−1)th stage shift register circuit, and a first clock signal for providing an enabled mth stage output signal in the mth period, wherein the mth stage shift register unit further is controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing the disenabled mth stage output signal in an (m+1)th period;
and
an mth stage control circuit controlled by the first clock signal for providing and outputting an mth stage second control signal to the (m−1)th stage shift register circuit according to the mth stage first control signal;
wherein m is a natural number greater than 1.

2 more elements

A gate driver used for driving a display panel, wherein the gate driver comprises:

a shift register comprising a plurality of multi-stage shift register circuits respectively used for outputting a plurality of shift output signals, wherein an mth stage shift register circuit of the multi-stage shift register circuits comprises:
an mth stage first node, wherein an mth stage first control signal enabled in an mth period is defined on the mth stage first node;
an mth stage shift register unit controlled by an (m−1)th stage output signal, which is provided by an (m−1)th stage shift register circuit and enabled in an (m−1)th period, and a first clock signal for providing an enabled mth stage output signal in the mth period, wherein the mth stage shift register unit further is controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing the disenabled mth stage output signal in an (m+1)th period;
and
an mth stage control circuit controlled by the first clock signal for providing and outputting an mth stage second control signal to the (m−1)th stage shift register circuit according to the mth stage first control signal;
wherein m is a natural number greater than 1.

3 more elements

Dependencies are inferred from the claim text.

Shift Register

Life of this patent

Shift Register

Life of this patent

Abstract

Claims19