Clock generator to reduce long term jitter

A clock generator comprising:

• a controller generating a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor;
• a digital phase locked loop (PLL) circuit generating a second internal clock signal in response to the low-frequency reference clock signal, the division factor and the first internal clock signal;
• a charge pump PLL circuit generating a plurality of third internal clock signals by using the second internal clock signal;
• and
• a divider generating a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals,
• wherein the divider comprises a plurality of phase divider circuits each generating four phase divided signals having a phase difference of 90°, wherein each phase divider circuit outputs two of the four phase divided signals to a subsequent phase divider circuit.

A clock generator comprising:

• a controller generating a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor;
• a digital phase locked loop (PLL) circuit generating a second internal clock signal in response to the low-frequency reference clock signal, the division factor and the first internal clock signal;
• a charge pump PLL circuit generating a plurality of third internal clock signals by using the second internal clock signal;
• and
• a divider generating a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals,
• wherein the divider comprises:
• a first selector selecting part of the third internal clock signals based on the phase selection signal and the division factor;
• a phase divider block generating a plurality of phase divided signals having different phases by using the selected third internal clock signals;
• and
• a second selector selecting one of the plurality of phase divided signals as the clock signal according to the third internal clock signals selected by the first selector.