Structure and method for latchup improvement using through wafer via latchup guard ring
AssigneeInternational Business Machines Corporation
InventorSteven H. VOLDMAN
Life of this patent
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Abstract
A method and structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.
Claims25
A method of manufacturing a semiconductor structure, comprising:
- forming a latchup sensitive structure;
- masking the latchup sensitive structure;
- flipping the latchup sensitive structure and substrate to gain access to an underside thereof;
- and
- etching a trough via through the substrate and adjacent the latchup sensitive structure using lithography and etching to isolate the latchup sensitive structure from at least an external source.
A method of forming a structure, comprising:
- forming at least a P+ diffusion structure that is sensitive to latchup;
- and
- forming a guard ring structure bounding the P+ diffusion structure to isolate the P+ diffusion structure from external sources.
A structure, comprising:
- a latchup sensitive structure;
- and
- a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.
A structure comprising:
- a latchup sensitive structure;
- and
- a guard ring that bounds the latchup sensitive structure to isolate the latchup sensitive structure from an external source.
A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising a latchup sensitive structure, and a guard ring that bounds the latchup sensitive structure to isolate the latchup sensitive structure from an external source.
Dependencies are inferred from the claim text.