US 2010/0244113 A1 · MOS VARACTOR AND FABRICATING METHOD OF THE SAME

Abstract

The present invention provides a MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, and a method of fabricating the MOS varactor. The MOS varactor include: island-like gate insulating layers which are arranged at equal intervals in the form of a (n×m) matrix (where, n and m are integers equal to or larger than one), and a gate electrode of a first height (t1) placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire of a second height (t2) (where, t1<t2), which is electrically connected to the gate contact; source/drain contacts which are arranged at equal intervals in a [(n+1)×(m+1)] matrix to form apexes of a square centered at the gate electrode and contact a doping region except for the bottom of the gate insulating layers; and a second metal wire of a third height (t3) (where, t2<t3), which is electrically connected to the source/drain contacts.

Claims19

Dependent claims

A MOS varactor comprising:

island-like gate insulating layers which are arranged at equal intervals in the form of a (n×m) matrix (where, n and m are integers equal to or larger than one), and a gate electrode of a first height (t1) placed on the gate insulating layers in a well region of a substrate;
a gate contact which contacts the gate electrode;
a first metal wire of a second height (t2) (where, t1<t2), which is electrically connected to the gate contact;
source/drain contacts which are arranged at equal intervals in a [(n+1)×(m+1)] matrix to form apexes of a square centered at the gate electrode and contact a doping region except for the bottom of the gate insulating layers;
and
a second metal wire of a third height (t3) (where, t2<t3), which is electrically connected to the source/drain contacts.

3 more elements

A method of fabricating a MOS varactor, comprising the steps of:

(a) forming a well region on a substrate and forming island-like gate insulating layers and a gate electrode over the gate insulating layers at equal intervals in the form of a (n×m) matrix (where, n and m are integers equal to or larger than one) in the well region;
(b) forming a doping region on the substrate except for the bottom of the gate insulating layers and depositing a first insulating layer covering the gate electrode;
(c) forming first contact holes connected to the gate electrode and second contact holes connected to the doping region on the first insulating layer, the second contact holes being arranged at equal intervals in a [(n+1)×(m+1)] matrix to form apexes of a square centered at the gate electrode;
(d) forming a gate contact with which the first contact holes are filled, a first source/drain contact with which the second contact holes are filled, and a first metal wire connected to the gate contact above the first insulating layer;
(e) depositing a second insulating layer which covers the first metal wire;
(f) forming third contact holes connected to the first source/drain contact on the second insulating layer;
and
(g) forming a second source/drain contact with which the third contact holes are filled, and a second metal wire connected to the second source/drain contact above the second insulating layer.

5 more elements

Dependencies are inferred from the claim text.

Mos varactor and fabricating method of the same

Life of this patent

Mos varactor and fabricating method of the same

Life of this patent

Abstract

Claims19