Thin film transistor, its manufacturing method, and liquid crystal display panel and electronic device using same
AssigneeNEC LCD Technologies, Ltd.
InventorKUNIHIRO SHIOTA
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Abstract
A thin film transistor (TFT) is provided which is capable of reducing leakage currents in a polycrystalline silicon TFT without causing an increase in manufacturing processes. Source/drain regions of an activated layer of the TFT to be formed in a circuit region and pixel region formed on a glass substrate of a liquid crystal display panel for a mobile phone is formed so that its boron impurity falls within a range of 2.5×1018/cm3 to 5.5×1018/cm3 and its impurity activation falls within a range of 1% to 7%.
Claims20
A thin film transistor comprising:
- a semiconductor layer formed on a substrate, said semiconductor layer comprising a polycrystalline semi-conductor;
- a gate electrode formed on said semiconductor layer with a gate insulating film interposed between said semiconductor layer and said gate electrode;
- and
- source/drain regions doped with an impurity formed in said semiconductor layer with said gate electrode being sandwiched between said source/drain regions,
- wherein impurity concentration in said source/drain regions is set to fall within a range of 2.5×1018/cm3 to 5.5×1018/cm3 and an activation rate of the impurity contained in said source/drain regions is set to fall within 1% to 7%.
An electronic device comprising:
- a thin film transistor, wherein said thin film transistor comprising:
- a polycrystalline semiconductor layer formed on a substrate;
- a gate electrode formed on said polycrystalline semi-conductor layer with a gate insulating film interposed between said polycrystalline semiconductor layer and said gate electrode;
- and
- source/drain regions doped with an impurity are formed in said polycrystalline semiconductor layer with said gate electrode being sandwiched between said source/drain regions;
- wherein impurity concentration in said source/drain regions is set to falls within a range of 2.5×1018/cm3 to 5.5×1018/cm3 and an activation rate of the impurity contained in said source/drain regions is set to fall within 1% to 7%.
A method for manufacturing a thin film transistor comprising:
- forming a polycrystalline silicon film by polycrystallizing an amorphous silicon film on a substrate and then etching said polycrystalline silicon film to form an activated layer of said thin film transistor;
- doping an impurity into source/ drain regions of said activated layer so that impurity concentration in said source/drain regions is set to falls within a range of 5.0×1018/cm3 to 5.5×1018/cm3;
- and
- annealing said source/drain regions so that an activation rate of the impurity is set to fall within 1% to 7%.
Dependencies are inferred from the claim text.