Registering a user-handler in hardware for transactional memory event handling

A processor comprising:

• a register capable of being updated by non-privileged level software to hold a reference to an address of a transactional handler;
• and
• execution logic to transfer a control flow to the transaction handler without intervention of privileged level software in response to a handler event during execution of a transaction based on the reference to the address of the transactional handler.

An apparatus comprising:

• a storage element capable of being updated by user-level software to specify a plurality of transactional handler events;
• and
• execution logic to vector execution from a transaction to a transactional handler in response to detecting a transactional handler event of the plurality of transactional handler events.

A system comprising:

• a processor including a user-addressable register to hold a reference to a transactional handler, a second register, and execution logic coupled to the first and the second register, wherein in response to a handler event during execution of a transaction, the execution logic is to update the second register with a reference to a current instruction location within the transaction, direct control flow to the transactional handler based on the reference to the transactional handler held in the user-addressable register to handle the handler event, and direct control flow back to the current instruction location based on the reference to the current instruction location held in the second register after execution of the transaction handler to handle the handler event;
• and
• an input/output (I/O) device coupled to the processor.