Processing Acceleration on Multi-Core Processor Platforms

A computer readable medium having stored thereon instructions to enable manufacture of a circuit comprising:

• a plurality of processing cores configured to perform an application task by executing certain operations in parallel in the plurality of processing cores and certain other operations serially within one or more of the plurality of processing cores;
• and
• an accelerator module modifying computer executable instructions of the application task program code to schedule sequential and parallel tasks across the plurality of processing cores by dividing the application task into a plurality of sub-blocks, determining a relative workload weight for each sub-block, and scheduling the sub-blocks for execution in a processing core of the plurality of processing cores depending upon a respective workload weight.

A multi-processor computing system comprising:

• a plurality of processing cores configured to perform an application task by executing certain operations in parallel in the plurality of processing cores and certain other operations serially within one or more of the plurality of processing cores;
• and
• an accelerator module modifying computer executable instructions of the application task program code to schedule sequential and parallel tasks across the plurality of processing cores by dividing the application task into a plurality of sub-blocks, determining a relative workload weight for each sub-block, and scheduling the sub-blocks for execution in a processing core of the plurality of processing cores depending upon a respective workload weight.