Distributed memory synchronized processing architecture

A data processing system comprising:

• a plurality of processors, each processor being coupled to a respective dedicated memory;
• and
• a voter module disposed between the plurality of processors and a peripheral, wherein each processor provides an I/O transaction to the voter module and the voter module determines whether a majority transaction is present among the I/O transactions received from the processors,
• wherein, if a majority transaction is present, the voter module releases the majority transaction to the peripheral,
• wherein, a processor error signal is output for any processor providing an I/O transaction not corresponding to the majority transaction, and
• wherein, if no majority transaction is determined, the system outputs a no majority transaction signal.

A method of operating a distributed memory synchronized processor system, the method comprising:

• independently executing software instructions on each of a plurality of processors, the software instructions being accessed by each processor from a respective dedicated memory;
• receiving at a transaction comparator disposed between the plurality of processors and a peripheral, a different I/O transaction from each of the processors;
• comparing, in the transaction comparator, each of the received I/O transactions to determine whether a majority transaction has been received;
• if a majority transaction was received, releasing, by the transaction comparator, the majority transaction to the peripheral;
• if a minority transaction was received from any processor, outputting an exception indicating the minority transaction;
• and
• if a majority transaction was not received, outputting an exception indicating that no majority transaction was received.