Transparent test method and scan flip-flop

A logic block having integral design-for-testability functionality, the logic block comprising:

• signal lines including a first control input, a second control input, a user data input, a scan data input, a user clock input, and a scan clock input;
• a core clocked D-type storage flip-flop including a core D input and a core clock input;
• a D-input selector configured to select between the user data input and the scan data input as a function of the first control input and to drive the core D input;
• a clock-input selector configured to select between the user clock input and the scan clock input as a function of the second control input and to drive the core clock input;
• wherein in a user mode, the logic block is configured to operate as a flip-flop macro in an application netlist specifying at least a portion of an integrated circuit;
• and
• wherein in a test mode, the logic block is configured to transparently operate as a scan chain irrespective of a value of the user data input or a value of the user clock input.

A method for operating a logic block having integral design-for-testability functionality, the method comprising:

• selecting between a user data input and a scan data input as a function of a first control input;
• driving a core D input of a core clocked D-type storage flip-flop of the logic block using the selected one of the user data input or the selected scan data input;
• selecting between a user clock input and a scan clock input as a function of a second control input based, at least in part, on an operation mode of the logic block, wherein, in a user mode, the user clock input is selected, and wherein, in a test mode, the scan clock input is selected;
• driving a core clock input of the core clocked D-type storage flip-flop using the selected one of the user clock input or the scan clock input;
• and
• detecting the presence of a fault, at least in part, on a core Q output of the core clocked D-type storage flip-flop.