System and method for detecting one or more winding paths for patterns on a reticle for the manufacture of semiconductor integrated circuits

A method for detecting invalid winding path in a layout design for the manufacture of electronic devices, the invalid winding path including one or more intersecting polygons, wherein the layout design includes at least one winding path to define one or more reticle patterns, the method comprising:

• obtaining a first winding path parameter;
• obtaining a second winding path parameter;
• defining a first reticle pattern in accordance with the first winding path parameter, the first winding path parameter having a first value;
• defining a second reticle pattern in accordance with the second winding path parameter, the second winding path parameter having a second value;
• comparing the first reticle pattern against the second reticle pattern;
• and
• outputting data associated with the comparing the first reticle pattern against the second reticle pattern.

A computer program product stored on a computer-read medium for detecting invalid winding path in a layout design, the invalid winding path including one or more intersecting polygons, wherein the layout design including at least one winding path to define one or more reticle patterns, the computer program product comprising:

• code for obtaining a first winding path parameter and a second winding path parameter;
• code for defining a first plurality of reticle patterns in accordance with the first winding path parameter, the first plurality of reticle patterns being associated with the least one winding path;
• code for defining a second plurality of reticle patterns in accordance with the second winding path parameter, the second plurality of reticle patterns being associated with the at least one winding path;
• code for comparing the first plurality of reticle patterns against the second plurality of reticle patterns;
• code for outputting a first plurality of data, the first plurality of data being associated with the comparing the first plurality of reticle patterns against the second plurality of reticle patterns.

A computer system for detecting invalid winding path in a layout design, the invalid winding path including one or more intersecting polygons, wherein the layout design including at least one winding path to define one or more reticle patterns, the computer system comprising:

• a data storage for storing a plurality of codes;
• a processor configured to execute the plurality of codes;
• and
• a user interface configured to receive a plurality of user inputs;
• wherein the plurality of codes comprises:
• code for receiving a first winding path parameter and a second winding path parameter from a user via the user interface;
• code for defining a first plurality of reticle patterns in accordance with the first winding path parameter, the first plurality of reticle patterns being associated with the least one winding path;
• code for defining a second plurality of reticle patterns in accordance with the second winding path parameter, the second plurality of reticle patterns being associated with the at least one winding path;
• code for comparing the first plurality of reticle patterns against the second plurality of reticle patterns, and
• code for outputting a first plurality of data, the first plurality of data being associated with the comparing the first plurality of reticle patterns against the second plurality of reticle patterns.

A method for facilitating semiconductor fabrication involving at least two entities, wherein a first entity of the at least two entities provides a layout design to a second entity of the at least two entities, the second entity manufacturing semiconductor chips in accordance with the layout design, the method comprising:

• the second entity providing a first winding path parameter and a second winding path parameter;
• the second entity generating a first plurality of reticle patterns and a second plurality of reticle patterns based on the layout design, wherein the first plurality of reticle patterns is based on a first value of the first winding path parameter, the second plurality of reticle patterns is based on a second value of the first winding path parameter;
• the second entity comparing the first plurality of reticle patterns and the second plurality of reticle patterns to ensure that the layout design does not contain invalid winding path including one or more intersecting polygons;
• and
• the second entity generating a first plurality of data based from the comparing the first plurality of reticle patterns and the second plurality of reticle patterns.

A method for manufacturing an integrated circuit device, the method comprising:

• providing a semiconductor wafer, the semiconductor wafer including a surface region;
• using at least one reticle to form a pattern on one or more portions of the surface region, the at least one reticle being manufactured using one or more error checking processes, the one or more error checking processes including:
• obtaining a first winding path parameter;
• obtaining a second winding path parameter;
• defining a first plurality of reticle patterns in accordance with the first winding path parameter and the second winding path parameter, the first winding path parameter having a first value, the first plurality of reticle patterns being associated with the least one winding path;
• defining a second plurality of reticle patterns in accordance with the second winding path parameter and the second winding path parameter, the first winding path parameter having a second value, the second plurality of reticle patterns being associated with the at least one winding path;
• comparing the first plurality of reticle patterns against the second plurality of reticle patterns;
• and
• outputting data associated with the comparing the first plurality of reticle patterns against the second plurality of reticle patterns.

A method for forming a reticle pattern from a layout design, comprising:

• providing a layout design in a layout design file;
• determining if the layout design file produces more than one reticle patterns;
• forming a reticle pattern if the layout design file produces an unique reticle pattern;
• and
• converting the reticle pattern to a machine recognizable file format for forming a photomask;
• and
• providing a warning if the layout design file produces more than one reticle patterns,
• wherein determining if the layout design file produces more than one reticle patterns comprising:
• using a first set of parameters to calculate a first winding path, the first winding path produces a first reticle pattern and a second set of parameters to calculate a second winding path, the second winding path produces a second reticle pattern;
• comparing the first reticle pattern and the second reticle pattern.