Storage circuit with fault detection and method for operating the same

A storage circuit with fault detection, comprising:

• a data input;
• an enable input;
• first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state, wherein the first fault detection circuit comprises a reset input, a set input and at least a first output, wherein the second fault detection circuit comprises a reset input, a set input and at least a second output, and wherein the first output is coupled to the set input of the second fault detection circuit and the second output is coupled to the set input of the first fault detection circuit;
• a first logic circuit configured to provide a reset signal to the reset input of the first fault detection circuit, and
• a second logic circuit configured to provide a reset signal to the reset input of the second fault detection circuit,
• wherein the first and the second logic circuits are configured to allow storing of a data signal applied to the data input if an enable signal is applied to the enable input and to prevent storage of the data signal applied to the data input if the enable signal is not applied to the enable input, and
• wherein the first output is indicative of the state of the first fault detection circuit and the second output is indicative of the state of the second fault detection circuit, wherein an invalid combination of the signal states at the first and second outputs indicates a fault.

A storage circuit with fault detection, comprising:

• a master-latch comprising:
• a data input;
• an enable input;
• a first and a second master-latch output;
• first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state, wherein the first fault detection circuit comprises a reset input, a set input and a first output forming the first master-latch output, and wherein the second fault detection circuit comprises a reset input, a set input and a second output forming the second master-latch output;
• a first logic circuit having inputs coupled to the data input and the enable input and an output coupled to the reset input of the first fault detection circuit;
• and
• a second logic circuit having inputs coupled to the data input and the enable input and an output coupled to the reset input of the second fault detection circuit;
• and
• a slave-latch comprising:
• a first and a second data input;
• an enable input;
• a first and a second slave-latch output;
• first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state, wherein the first fault detection circuit comprises a reset input, a set input and a first output forming the first slave-latch output, and wherein the second fault detection circuit comprises a reset input, a set input and at least a second output forming a second slave-latch output;
• a first logic circuit having an input coupled to the first data input of the slave-latch and a second input coupled to the enable input of the slave-latch and an output coupled to the reset input of the first fault detection circuit at the slave-latch;
• and
• a second logic circuit having an input coupled to the second data input and a second input coupled to the enable input of the slave-latch and an output coupled to the reset input of the second fault detection circuit of the slave-latch;
• wherein the first master-latch output is coupled to the first data input of the slave-latch and the second master-latch output is coupled to the second data input of the slave-latch, and wherein the enable input of the master-latch is adapted to receive an enable signal and wherein the enable input of the slave-latch is adapted to receive an inverted version of the enable signal.

A method for operating a storage circuit with fault detection, wherein the storage circuit comprises a data input, an enable input, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state, a first output of the first fault detection circuit indicative of the state of the first fault detection circuit and a second output indicative of the state of the second fault detection circuit, the method comprising:

• applying a data signal to the data input to bring the first fault detection circuit into the first stable state and the second fault detection circuit into the second stable state;
• and
• monitoring signal states at the first output of the first fault detection circuit and at the second output of the second fault detection circuit,
• wherein an invalid logic combination of the signal states at the first and second outputs indicates a fault and a valid logic combination of the signal states at the first and second outputs indicates valid stored data.

A storage circuit with fault detection, comprising:

• first and second fault detection means for detecting a fault, each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection means is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state;
• a data input;
• means for causing the first fault detection means to assume the first stable state and the second fault detection means to assume the second stable state to store a data signal applied to the data input;
• and
• a first output indicative of the state of the first fault detection means and a second output indicative of the state of the second fault detection means, wherein an invalid combination of the signal states at the first and second outputs indicates a fault.