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AssigneePanasonic Corporation
InventorHiroyuki MOTOZUKA
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A soft output decoder capable of performing decoding with a small computational complexity necessary for likelihood calculation thereby to reduce the scale of the operation circuit and to shorten the processing delay time. The soft output decoder (100) comprises a &ggr;α calculating section (101), timing adjusters (102, 103), a &ggr;β calculation section (104), and a &Lgr; calculating unit (110). The &Lgr; calculating unit (110) is composed of a hard decision decoding section (111), a loss likelihood calculating section (112), a win likelihood storage section (113), and a subtractor (114). The likelihoods determined by a Max-log-MAP decoder are separated into win likelihoods and loss likelihoods, and only the loss likelihoods are calculated. A hard decision decoding section (111) for sequentially specifying the states through which the maximum likelihood path passes is used for a method for distinguishing the win and loss likelihoods.
A soft output decoder that receives code words corresponding to a plurality of information words and calculates soft decision decoding results of the information words from a plurality of likelihood values corresponding to a plurality of candidate values adopted by the information words, the soft output decoder comprising:
The soft output decoder comprising:
A soft decision value calculating method for receiving code words corresponding to a plurality of information words and calculating soft decision decoding results of the information words from a plurality of likelihood values corresponding to a plurality of candidate values adopted by the information words, the soft decision value calculating method comprising:
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