Low density parity check code row update instruction
AssigneeTexas Instruments Incorporated
InventorsEric BISCONDI, David J. HOYLE, Tod D. WOLF
Life of this patent
Estimating the term…
Loading patent…
AssigneeTexas Instruments Incorporated
InventorsEric BISCONDI, David J. HOYLE, Tod D. WOLF
Estimating the term…
Apparatus for optimizing low-density parity check (“LDPC”) decoding in a processor is disclosed herein. A processor in accordance with the present disclosure includes an LDPC decoder row update execution unit. The LDPC decoder row update execution unit accelerates an LDPC row update computation by performing a logarithm estimation and a magnitude minimization in parallel. The execution unit is activated by execution of an LDPC row update instruction. The execution unit adds a minimum of magnitudes of two input values to a difference of estimated logarithms of exponential functions of a sum and a difference of the two input values to produce a row update value.
A processor, comprising:
A system, comprising:
A low density parity check (“LDPC”) code decoder, comprising:
A method, comprising:
Dependencies are inferred from the claim text.