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US 2010/0169728 A1Published application
Decoupled clocking in testing architecture and method of testing
AssigneeIntel Corporation
InventorsDavid Dehnert, Matthew Heath
Life of this patent
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Abstract
A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.
Claims15
A test architecture comprising:
- a first logic block having a plurality of first scan chains;
- and
- a first scan controller including:
- a first clock domain crossing circuit to process an exchange of an input test data packet and an output test data packet between the first scan controller and a test access mechanism which are operated by different clock sources,
- a first decoding circuit to generate a first test stimulus from the input test data packet, and
- a first input staging circuit and a first output staging circuit to process an exchange of the first test stimulus and a first test response between the first scan controller and the first scan chains of the first logic block.
3 more elements
A method of testing, comprising:
- connecting a test access mechanism to a plurality of scan controllers which are coupled to a plurality of logic blocks having different scan chain designs;
- deactivating a functional clock of a first of the logic blocks;
- transmitting an input test data packet from the test access mechanism to a first of the scan controllers, wherein the test access mechanism and the first of the scan controllers are operated by different clock sources;
- applying a first test stimulus, generated from the input test data packet, to the first of the logic blocks;
- activating the functional clock of the first of the logic blocks for at least one clock cycle;
- receiving a first test response from the first of the logic blocks;
- and
- transmitting an output test data packet from the first of the scan controllers to the test access mechanism.
5 more elements
Dependencies are inferred from the claim text.