Eda tool, semiconductor device, and scan chain configuration method

An EDA tool comprising:

• an expected value derivation module for deriving an expected value of each flip-flop of a semiconductor device to be verified by the EDA tool;
• a grouping module for grouping each flip-flop into a plurality of groups, based on the expected value of each flip-flop of the semiconductor device subject to verification;
• and
• a scan chain configuration module for pairing two groups among the groups, reversing polarity of each flip-flop belonging to one group of the pair, and configuring a scan chain of each pair,
• the EDA tool being able to call the expected value derivation module, the grouping module, and the scan chain configuration module.

A scan chain configuration method by an EDA tool which can call an expected value derivation module, a grouping module, and a scan chain configuration module, the scan chain configuration method comprising:

• an expected value derivation step of deriving, by the expected value derivation module, an expected value of each flip-flop of a semiconductor device subject to verification;
• a step width readout step of reading, by the grouping module, a step width of a group;
• a grouping step of determining, by the grouping module, which group corresponding to the step width each flip-flop of the semiconductor device subject to verification belongs to;
• and
• a scan chain configuration step of configuring, by the scan chain configuration module, a scan chain with flip-flops in a group assigned in the grouping step.

A scan chain configuration method by an EDA tool which can call an expected value derivation module, a grouping module, and a scan chain configuration module, the scan chain configuration method comprising:

• an expected value derivation step of deriving, by the expected value derivation module, an expected value of each flip-flop of a semiconductor device subject to verification;
• a step width readout step of reading, by the grouping module, a step width of a group;
• a grouping step of determining, by the grouping module, which group corresponding to the step width each flip-flop of the semiconductor device subject to verification belongs to;
• a pair configuration step of pairing two groups among groups formed in the grouping step;
• a polarity reversal step of reversing, by the scan chain configuration module, polarity of each flip-flop of one group included in a pair formed in the pair configuration step;
• and
• a scan chain configuration step of configuring a scan chain of each pair by unifying the one group in which the polarity of each flip-flop is reversed in the polarity reversal step and the other group in which polarity of each flip-flop is not reversed.