Memory module tester
AssigneeSamsung Electronics Co., Ltd.
InventorsJung Kuk Lee, Seung Hee Mun, Seung Jin Seo, Woo-Jin Na
Life of this patent
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Abstract
a memory module test system for testing a plurality of memory modules includes a plurality buffers in one-to-one correspondence the plurality of memory modules, each of the buffers including a self-test engine for testing a corresponding memory module. The test system further includes an interface configured to receive a test program for testing the memory module, and a gate array configured to transmit the test program to the buffers using a Joint Test Action Group (JTAG) protocol and to read test results of the test program from the buffers using the JTAG protocol.
Claims14
A memory module test system for testing a plurality of memory modules, comprising:
- a plurality buffers in one-to-one correspondence the plurality of memory modules, each of the buffers including a self-test engine for testing a corresponding memory module;
- an interface configured to receive a test program for testing the memory module;
- and
- a gate array configured to transmit the test program to the buffers using a predetermined test protocol and to read test results of the test program from the buffers using the predetermined test protocol.
A memory module tester comprising:
- a socket for receiving a memory module to be tested;
- a buffer operatively coupled to the socket;
- an interface configured to receive a test program for testing the memory module;
- and
- a gate array configured to transmit the test program to the buffer using a predetermined test protocol and test results of the test program from the buffers using the predetermined test protocol.
Dependencies are inferred from the claim text.