Memory control apparatus, memory optimization program product, and memory optimization method

A computer program product for memory optimization comprising a computer readable medium comprising programmed instructions, wherein the instructions, when executed by a computer, cause the computer to:

• generate a plurality of delay clock signals comprising delay times different from each other by delaying a clock signal comprising a rise portion and a fall portion that appear in a predetermined cycle;
• extracting data of portions from a data signal comprising predetermined reference data, the portions corresponding to the rise or fall portions of generated delay clock signals;
• first determining whether each data extracted coincides with the reference data;
• and
• second determining a range of the delay time with respect to the rise portion of the clock signal and a range of the delay time with respect to the fall portion of the clock signal from the delay times of the delay clock signals corresponding to the data that have been determined in the first determining to coincide.

A memory optimization method, comprising:

• generating a plurality of delay clock signals comprising delay times different from each other by delaying a clock signal having a rise portion and a fall portion that appear in a predetermined cycle;
• extracting data of portions corresponding to the rise or fall portions of generated delay clock signals, from a data signal comprising predetermined reference data;
• first determining whether each data extracted coincides with the reference data;
• and
• second determining a range of the delay time with respect to the rise portion of the clock signal and a range of the delay time with respect to the fall portion of the clock signal from the delay times of the delay clock signals corresponding to the data that have been determined in the first determining to coincide.