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US 2010/0169700 A1Published application
Adaptive clock enable for memory control
OwnerPhilip Abraham, Steve Kulick +1inventors
InventorsPhilip Abraham, Steve Kulick, Mahadev Nemani
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Abstract
In some embodiments a memory rank idle counter enables de-assertion of a clock enable signal of a rank of a memory for idle systems. Clock enable signal assertion is maintained when there is a lot of traffic to the memory rank. A memory rank idle time prediction counter transfers a value to the memory rank idle counter when the memory rank is idle. Other embodiments are described and claimed.
Claims17
An apparatus comprising:
- a memory rank idle counter to enable de-assertion of a clock enable signal of a rank of a memory for idle systems and to keep the clock enable signal asserted when there is a lot of traffic to the memory rank;
- and
- a memory rank idle time prediction counter to transfer a value to the memory rank idle counter when the memory rank is idle.
A system comprising:
- a memory including a clock enable signal of a rank of the memory;
- and
- a memory controller including:
- a memory rank idle counter to enable de-assertion of the clock enable signal of a rank of a memory for idle systems and to keep the clock enable signal asserted when there is a lot of traffic to the memory rank;
- and
- a memory rank idle time prediction counter to transfer a value to the memory rank idle counter when the memory rank is idle.
3 more elements
A method comprising:
- enabling de-assertion of a clock enable signal of a rank of a memory for idle systems;
- and
- keeping the clock enable signal asserted when there is a lot of traffic to the memory rank.
Dependencies are inferred from the claim text.