Processor register recovery after flush operation

A processor, comprising:

• a fetch unit that fetches a plurality of instructions from an instruction source;
• a decoder/dispatcher that decodes the plurality of instructions, the plurality of instructions including instructions that reference a target register of a general purpose register for storage of results thereof, the instructions that reference the target register including a current instruction and previous instructions, wherein the decoder/dispatcher dispatches the plurality of instructions to an issue queue that is coupled to the dispatcher;
• a general purpose register, coupled to the dispatcher, that stores a state of the processor;
• a plurality of execution units, coupled to the issue queue, wherein the issue queue issues the plurality of instructions that reference the particular target register out-of-order to the execution units;
• a recovery buffer unit, coupled to the general purpose register, that stores a respective entry for each of the previous instructions and the current instruction, the previous instructions and the current instruction referencing the same target register, wherein the execution units speculatively execute the previous instructions and the current instruction;
• a branch execution unit, coupled to the issue queue, that determines if an exception occurred for one of the previous instructions that requires an issue queue flush, wherein the issue queue performs an issue queue flush if the exception occurred;
• and
• wherein the recovery buffer unit, in response to the issue queue flush, performs a recovery buffer unit recovery to determine an oldest valid entry of the recovery buffer unit, the recovery buffer unit restoring the general purpose register to a known good state using the result of a target register corresponding to the oldest valid entry of the recovery buffer unit.

An information handling system (IHS), comprising:

• a memory;
• a processor, coupled to the memory, the processor including:
• a fetch unit that fetches a plurality of instructions from an instruction source;
• a decoder/dispatcher that decodes the plurality of instructions, the plurality of instructions including instructions that reference a target register of a general purpose register for storage of results thereof, the instructions that reference the target register including a current instruction and previous instructions, wherein the decoder/dispatcher dispatches the plurality of instructions to an issue queue that is coupled to the dispatcher;
• a general purpose register, coupled to the dispatcher, that stores a state of the processor;
• a plurality of execution units, coupled to the issue queue, wherein the issue queue issues the plurality of instructions that reference the particular target register out-of-order to the execution units;
• a recovery buffer unit, coupled to the general purpose register, that stores a respective entry for each of the previous instructions and the current instruction, the previous instructions and the current instruction referencing the same target register, wherein the execution units speculatively execute the previous instructions and the current instruction;
• a branch execution unit, coupled to the issue queue, that determines if an exception occurred for one of the previous instructions that requires an issue queue flush, wherein the issue queue performs an issue queue flush if the exception occurred;
• and
• wherein the recovery buffer unit, in response to the issue queue flush, performs a recovery buffer unit recovery to determine an oldest valid entry of the recovery buffer unit, the recovery buffer unit restoring the general purpose register to a known good state using the result of a target register corresponding to the oldest valid entry of the recovery buffer unit.