Efficient Encoding for Detecting Load Dependency on Store with Misalignment

A processor comprising:

• a data cache configured to store data in units of cache blocks;
• and
• a load/store unit coupled to the data cache and comprising a store queue, wherein the load/store unit is configured to allocate a first entry in the store queue to a store memory operation, wherein the load/store unit is configured to write the first entry with a first block address, a plurality of offsets, and a plurality of masks corresponding to the store memory operation, wherein the first block address identifies a first cache block in memory, and wherein the store memory operation updates one or more bytes in the first cache block;
• wherein a cache block comprises a plurality of byte ranges, and wherein each of the plurality of offsets identifies a byte range of the plurality of byte ranges in the first cache block that is updated by the store memory operation, and wherein a corresponding one of the plurality of masks identifies which bytes in the identified byte range are updated by the store memory operation;
• and
• wherein the load/store unit is configured to detect whether or not a load memory operation reads at least one byte updated by the store memory operation responsive to the first block address, the plurality of offsets, the plurality of masks, a second block address corresponding to the load memory operation, a second plurality of offsets corresponding to the load memory operation, and a second plurality of masks corresponding to the load memory operation.

A method comprising:

• writing a first address, a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to a store memory operation to a first entry in a queue, wherein a cache block is logically divided into alternately-addressed even and odd byte ranges, wherein a number of bytes in each byte range is an integer greater than one, and wherein a given store memory operation writes at most one even byte range and one adjacent odd byte range;
• and wherein the first even offset identifies a first even byte range in the cache block that is potentially written by the store memory operation and the first odd offset identifies a first odd byte range in the cache block that is potentially written by the store memory operation;
• and wherein the first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation;
• receiving an input address, an input even offset, an input even mask, an input odd offset, and an input odd mask that each correspond to a load memory operation;
• determining that the store memory operation writes at least one byte read by the load memory operation responsive, at least in part, to the first address equaling the input address and at least one of:
• (i) the first even offset equaling the first odd offset and the first even mask overlapping the input even mask;
• or (ii) the first odd offset equaling the input odd offset and the first odd mask overlapping the input odd mask.