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US 2010/0169614 A1Published application
Processor for executing highly efficient vliw
AssigneePanasonic Corporation
InventorsShuichi TAKAYAMA, Nobuo Higaki
Life of this patent
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Abstract
A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.
Claims22
1-29. (canceled)
A VLIW processor, comprising:
- fetch means for fetching an instruction that includes a plurality of operation fields;
- and
- a decoder unit for decoding the plurality of operation fields in the fetched instruction in parallel with each other;
- the VLIW processor being characterized in that:
- the plurality of operation fields are categorized into two types, a first type of operation field and a second type of operation field,
- the first type of operation field is composed of a condition code with no operand thereof,
- the second type of operation field is composed of an operation code and one or more operands, and
- the decoder unit includes:
- a first decoder for decoding the condition code in the first type of operation field, and
- a second decoder for decoding the operation code in the second type of operation field.
7 more elements
Dependencies are inferred from the claim text.