Read and write monitoring attributes in transactional memory (tm) systems

A processor comprising:

• a user-accessible register to hold a non-selective value to indicate a non-selective mode of operation of the processor and a selective value to indicate a selective mode of operation of the processor;
• control logic coupled to the user-accessible register to determine if a memory access operation is to be monitored based on a selection criteria in response to the user-accessible register holding the selective value;
• and
• a hardware attribute to track the memory access operation to memory in response to the user-accessible register holding the non-selective value or the control logic determining the memory access operation is to be monitored based on the selection criteria.

An apparatus comprising:

• logic to encounter a memory access operation referencing a memory address associated with a data item that is to be monitored;
• a data array of a cache memory including a plurality of lines, wherein a number of lines of the plurality of lines is to hold the data item responsive to the logic encountering the memory access operation;
• and
• a coherency state array of the cache memory including a state entry corresponding to each of the plurality of lines, wherein each of the state entries, which correspond to the number of lines to hold the data item, are to be updated to represent a monitored coherency state in response to the first number of lines to holding the data item.

A system comprising:

• a processor including
• a cache memory to hold a data item referenced by a transactional memory access operation to be executed by the processor;
• hardware attributes associated with the cache memory to represent an access state of the data item at a granularity of the data item unaligned from lines of the cache memory in response to the processor executing the memory access operation, wherein the access state is to be associated with a type of the transactional memory access operation;
• and
• a system memory to be coupled to the processor to hold an un-cached copy of the data item.

A method comprising:

• determining if a memory access operation referencing a data item is to be monitored;
• caching the data item in a number of lines of a cache;
• and
• in response to determining the memory access operation is to be monitored,
• determining hardware attributes associated with the cache to bound the data item;
• and
• updating the hardware attributes to represent an access state associated with a type of the memory access operation.