Cache control device and control method

A cache control device that controls access requests to a cache shared by plural threads that are simultaneously executed, the cache control device comprising:

• a storing unit provided in association with each of the threads, the storing unit storing a flag that indicates a first defined value when the thread enters execution of an atomic instruction for indivisibly executing plural kinds of processing and indicates a second defined value different from the first defined value when the atomic instruction to be executed is completed and storing, when the thread enters execution of the atomic instruction, address information of an access destination of the atomic instruction to be executed;
• a determining unit for determining, when an access request is issued from a certain thread, referring to the flag value stored by the storing unit, whether a thread different from the thread that issues the access request is executing an atomic instruction and, further, determining, when it is determined that the different thread is executing the atomic instruction, referring to the address information stored by the storing unit, whether the address information of the access destination of the atomic instruction being executed by the different thread and address information designated by the issued access request coincide with each other;
• and
• an executing unit for executing, when the determining unit determines that the different thread is executing the atomic instruction and determines that the address information of the access destination of the atomic instruction being executed by the different thread and the address information designated by the issued access request coincide with each other, processing for putting the issued access request on standby.

A cache control method executed by a cache control device that controls access requests to a cache shared by plural threads that are simultaneously executed, the cache control method comprising:

• adopting a configuration including a storing unit provided in association with each of the threads, the storing unit storing a flag that indicates a first defined value when the thread enters execution of an atomic instruction for indivisibly executing plural kinds of processing and indicates a second defined value different from the first defined value when the atomic instruction is completed,
• writing the first defined value in a relevant flag stored in the storing unit when the thread enters execution of the atomic instruction and writing the second defined value when the atomic instruction is completed;
• determining, when an access request is issued from a certain thread, referring to the flag value stored by the storing unit, whether a thread different from the thread that issues the access request is executing an atomic instruction;
• and
• executing, when it is determined according to the determination processing that the different thread is executing the atomic instruction, processing for putting the issued access request on standby.

A cache control method executed by a cache control device that controls access requests to a cache shared by plural threads that are simultaneously executed, the cache control method comprising:

• adopting a configuration including storing unit provided in association with each of the threads, the storing unit storing a flag that indicates a first defined value when the thread enters execution of an atomic instruction for indivisibly executing plural kinds of processing and indicates a second defined value different from the first defined value when the atomic instruction to be executed is completed and storing, when the thread enters execution of the atomic instruction, address information of an access destination of the atomic instruction to be executed, the cache control device writing the first defined value in a relevant flag stored in the storing unit and writing the address information of the access destination of the atomic instruction in the storing unit when the thread enters execution of the atomic instruction and writing the second defined value in the flag when the atomic instruction is completed;
• determining, when an access request is issued from a certain thread, referring to the flag value stored by the storing unit, whether a thread different from the thread that issues the access request is executing an atomic instruction and, further, determining, when it is determined that the different thread is executing the atomic instruction, referring to the address information stored by the storing unit, whether the address information of the access destination of the atomic instruction being executed by the different thread and address information designated by the issued access request coincide with each other;
• and
• executing, when it is determined according to the determination processing that the different thread is executing the atomic instruction and determines that the address information of the access destination of the atomic instruction being executed by the different thread and the address information designated by the issued access request coincide with each other, processing for putting the issued access request on standby.