Semiconductor memory device, data transfer device, and method of controlling semiconductor memory device

A data transfer device that transfers data by using a second memory as a cache for transferring data between a nonvolatile first memory and a host device, the data transfer device comprising:

• a first controller that controls a first data transfer in which data are transferred from the first memory to the second memory in predetermined transfer units;
• a second controller that controls a second data transfer in which data are transferred from the second memory to the host device;
• and
• a control unit that, upon receipt of a read request from the host device, outputs to the first controller a read instruction in which an address in the second memory being a transfer-destination address of the first data transfer is specified for each of the predetermined transfer units, and creates a descriptor in which the addresses in the second memory being transfer-source addresses of the second data transfer are specified in order of transfer, wherein
• the first controller outputs an end notification to the second controller at each end of the first data transfer, and the second controller executes the second data transfer according to the specification in the descriptor after receiving the end notification.

A method of controlling a semiconductor memory device that includes:

• a nonvolatile first memory;
• a second memory used as a cache for transferring data between the first memory and a host device;
• a first controller that controls a first data transfer in which data are transferred from the first memory to the second memory in predetermined transfer units;
• and a second controller that controls a second data transfer in which data are transferred from the second memory to the host device,
• the method comprising:
• upon receipt of a read request from the host device, outputting to the first controller a read instruction in which an address in the second memory being a transfer-destination address of the first data transfer is specified for each of the predetermined transfer units and creating a descriptor in which the addresses in the second memory being transfer-source addresses of the second data transfer are specified in order of transfer;
• causing the first controller to output an end notification to the second controller at each end of the first data transfer;
• and
• causing the second controller to execute the second data transfer according to the specification in the descriptor after receiving the end notification.