US 2010/0169546 A1 · FLASH MEMORY ACCESS CIRCUIT

Abstract

A system comprises an instruction processor (10), a flash memory device (14a), a flash control circuit (14) and a working memory (16). Instructions of an interrupt program are kept stored in the flash memory device (14a). When the instruction processor (10) receives an interrupt signal, the instruction processor (10) executes loading instructions, to cause the flash control circuit (14) to load said instructions of the interrupt program from the flash memory device (14a) into the working memory (16). The instructions of the interrupt program are subsequently executed with the instruction processor (10) from the working memory (16). Preferably it is tested whether a copy of said instructions of the interrupt program is stored in the working memory (16) at the time of the interrupt. If the copy is found stored, execution of said instructions from the copy is started before completing execution of of access instructions that were in progress at the time of the interrupt. If the copy is not found stored, execution of the access instructions is first completed and subsequently the instruction processor (10) executes the loading instructions, followed by execution of the instructions of the copy of interrupt program from the working memory (16).

Claims21

Dependent claims

A flash memory access circuit, comprising:

a flash interface port (301) for accessing a flash memory device (14a);
a working memory (16) coupled to said flash interface;
a flash control circuit (14);
and
an instruction processor (10) coupled to said working memory (16) and the flash control circuit (14), the instruction processor (10) having an interrupt input, the instruction processor (10) being programmed to handle an interrupt signaled at the interrupt input by executing loading instructions to cause the flash control circuit to load a copy of instructions of an interrupt program from the flash memory (14a) via said flash interface for storage into the working memory (16) and subsequently to handle the interrupt by executing the instructions of the copy from the working memory (16).

2 more elements

A flash memory access circuit, comprising:

a flash interface port (301) for accessing a flash memory device (14a);
a working memory coupled to said flash interface (16);
a flash control circuit (14);
and
an instruction processor (10) coupled to said working memory (16) and the flash control circuit (14), wherein the instruction processor is programmed to represent a queue of successively received requests to access the flash memory device (14a) and to execute a respective series of request handling instructions in response to each of the requests, the request handling instructions being for causing the flash control circuit (14a) to process respective stages of handling the successively access requests, instruction processor (10) being programmed to select a sequence of execution of the request handling instructions for different requests so that the flash control circuit (14) is made to operate in pipelined fashion in conformance with a sequence in which the requests have been added to the queue.

2 more elements

A method of operating a system that comprises an instruction processor (10), a flash memory device (14a), a flash control circuit (14) and a working memory (16), the method comprising:

keeping instructions of an interrupt program stored in the flash memory device (14a);
receiving an interrupt signal at the instruction processor (10);
using execution of loading instructions by the instruction processor (10) in response to the interrupt signal to cause the flash control circuit (14) to load said instructions of the interrupt program from the flash memory device (14a) into the working memory (16);
executing said instructions of the interrupt program with the instruction processor (10) from the working memory (16).

1 more element

Dependencies are inferred from the claim text.

Flash memory access circuit

Life of this patent

Flash memory access circuit

Life of this patent

Abstract

Claims21