Multi-port system and method for routing a data element within an interconnection fabric

A device, comprising:

• a first circuit configured to couple between a first bus and a link, wherein the link is coupled to a second bus by a second circuit, wherein the first and second circuits are independently operable bridge devices, wherein a first plurality of devices are coupled to and compatible with the first bus, and wherein a second plurality of devices are coupled to and compatible with the second bus;
• wherein the first circuit is configured to:
• send outgoing information serially through the link in a form different from that used by the first bus and the second bus;
• and
• allow a host processor to communicate over the first bus to individually address different ones of the second plurality of devices, wherein communication between the host processor and a first one of the second plurality of devices uses a type of addressing used by the host processor to address ones of the first plurality of devices via the first bus, and wherein communication between the host processor and the first one of the second plurality of devices does not employ a second, intervening one of the second plurality of devices.

A system, comprising:

• a host processor;
• a link;
• a first bus;
• a second bus;
• a first circuit coupled between the first bus and the link;
• a first plurality of devices coupled to and compatible with the first bus;
• a second circuit coupled between the link and the second bus;
• a second plurality of devices coupled to and compatible with the second bus;
• wherein the first circuit and the second circuit are each configured to independently operate as bridge devices, and wherein the first circuit is configured to:
• send information serially through the link in a form different from that used by the first bus and the second bus;
• and
• allow the host processor to communicate over the first bus to individually address different ones of the second plurality of devices, wherein communication between the host processor and a first one of the second plurality of devices uses a type of addressing used by the host processor to address ones of the first plurality of devices via the first bus, and wherein communication between the host processor and the first one of the second plurality of devices does not employ a second, intervening one of the second plurality of devices.