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US 2010/0169532 A1Published application
System lsi having plural buses
AssigneeFujitsu Microelectronics Limited
InventorsShinichi SUTOU, Kiyomitsu Katou
Life of this patent
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Abstract
A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories.
Claims20
A system LSI comprising:
- first and second memories;
- first and second buses;
- a bus bridge that performs signal transfer between the first and second buses;
- a first bus system connecting to the first bus and accessing the first or second memory;
- a second bus system connecting to the second bus and accessing the first or second memory;
- a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories, wherein:
- the memory access circuit has
- a first access path that connects the first bus-side input/output terminal and the first memory-side input/output terminal;
- a second access path that connects the second bus-side input/output terminal and the second memory-side input/output terminal;
- a third access path that connects the first bus-side input/output terminal and the second memory-side input/output terminal;
- and
- a fourth access path that connects the second bus-side input/output terminal and the first memory-side input/output terminal;
- and
- the memory access circuit
- performs signal transfer through the first to fourth access paths;
- and
- for memory access by the first or second bus system, selects at least one of the first to fourth access paths in accordance with a path-selection-mode setting signal from the first or second bus system.
14 more elements
A system LSI having first and second memories, the system comprising:
- a multilayer bus having plural independent buses;
- a first bus system connecting to the multilayer bus and accessing the first or second memory;
- a second bus system connecting to the multilayer bus and accessing the first or second memory;
- a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from a selected bus of the multilayer bus and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories, wherein:
- the memory access circuit has
- a first access path that connects the first bus-side input/output terminal and the first memory-side input/output terminal;
- a second access path that connects the second bus-side input/output terminal and the second memory-side input/output terminal;
- a third access path that connects the first bus-side input/output terminal and the second memory-side input/output terminal;
- and
- a fourth access path that connects the second bus-side input/output terminal and the first memory-side input/output terminal;
- and
- the memory access circuit performing signal transfer through the access path,
- for memory access by the first or second bus system, selects at least one of the first to fourth access paths in accordance with a path-selection-mode setting signal from the first or second bus system.
10 more elements
A system LSI comprising:
- connecting a first bus system to a first bus;
- accessing a first or second memory with the first bus system;
- connecting a second bus system to a second bus;
- accessing the first or second memory with the second bus system;
- transferring signals to/from the first and second buses with a memory access circuit having first and second bus-side input/output terminals;
- transferring signals to/from the first and second memories with first and second memory-side input/output terminals;
- connecting the first bus-side input/output terminal to the first memory-side input/output terminal with a first access path in the memory access circuit;
- connecting the second bus-side input/output terminal to the second memory-side input/output terminal with a second access path in the memory access circuit;
- connecting the first bus-side input/output terminal to the second memory-side input/output terminal with a third access path in the memory access circuit;
- connecting the second bus-side input/output terminal to the first memory-side input/output terminal with a fourth access path in the memory access circuit;
- and
- selecting at least one of the first to fourth access paths in accordance with a path-selection-mode setting signal from the first or second bus system;
- and
- accessing the memory by the first or second bus system.
11 more elements
Dependencies are inferred from the claim text.