System, an apparatus and a method for performing chip-level electrostatic discharge simulations

A method of simulating ESD behavior of an integrated circuit (IC), comprising:

• identifying circuitry and ESD cells of said IC;
• generating linear models of said identified circuitry and said identified ESD cells based on physical attributes associated therewith;
• and
• simulating said IC under ESD conditions employing said linear models.

An ESD simulation system for integrated circuits (ICs) comprising:

• a predefined ESD protection element database configured to store technology-independent topologies of ESD protection elements wherein each of said topologies has a defined set of attributes for each pair of terminals thereof;
• an ESD protection element attributes database configured to store technology-dependent protection cell physical attributes associated with said ESD protection elements;
• a predefined circuit database configured to store topologies of circuitry wherein each of said topologies has a defined set of attributes for each pair of terminals thereof;
• a circuit attributes database configured to store circuitry physical attributes associated with said circuitry topologies;
• and
• an ESD modeler, including:
• a circuit analyzer configured to provide identified ESD cells and circuitry of said IC by comparing component information of said IC with said predefined ESD protection elements and said predefined circuit topologies;
• and
• a model generator configured to create linearized models of said identified ESD cells and said identified circuitry based on said protection cell physical attributes associated with said identified ESD cells and said circuitry physical attributes associated with said identified circuitry, wherein a combination of said linearized models represent operation of said identified ESD cells and said circuitry under ESD conditions.