Reducing warpage for fan-out wafer level packaging
AssigneeSTMicroelectronics Asia Pacific Pte Ltd
InventorsYonggang Jin, Xavier Baraton, Faxing Che
Life of this patent
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Abstract
Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.
Claims24
A method of manufacturing fan-out wafer level packaging, the method comprising:
- positioning an integrated circuit on a first surface;
- forming a layer of encapsulant on the first surface substantially surrounding the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit;
- forming a redistribution layer configured to electrically couple a bond pad of the integrated circuit to a redistributed bond pad;
- and
- forming a bump at the redistributed bond pad.
The method of claim 9, wherein forming the redistribution layer includes forming the redistribution layer over at least a portion of the first dielectric layer, and filling at least partially the bond pad via with a portion of the redistribution layer.
The method of claim 11, wherein the redistribution layer includes the redistributed bond pad, and wherein forming the bump includes forming the bump in direct contact with the redistribution layer.
A method of manufacturing fan-out wafer level packaging, the method comprising:
- positioning an active surface of an integrated circuit on a first surface;
- placing an inactive surface of the integrated circuit in an encapsulant in a molding chamber;
- and
- compressing the first surface towards the encapsulant in the molding chamber to cover all sides of the integrated circuit with encapsulant and to prevent the encapsulant from covering the inactive surface and the active surface of the integrated circuit.
A method of forming an encapsulation layer for fan-out wafer level packaging, comprising:
- positioning a first surface of an integrated circuit on a carrier;
- and
- compressing the integrated circuit into a molding chamber having an encapsulant therein, the molding chamber sized and shaped to allow a second surface of the integrated circuit to contact a bottom surface of the molding chamber.
Dependencies are inferred from the claim text.