Method for fabricating semiconductor device
AssigneePanasonic Corporation
InventorNobuo AOI
Life of this patent
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Abstract
At least three or more plurality of chips are stacked to form a three-dimensional integrated circuit. When the plurality of chips are stacked, at least two or more of three stacking methods are used which are a wafer-to-wafer stacking method that bonds together the mutually corresponding chips each on a wafer level, a chip-to-wafer stacking method that bonds together the mutually corresponding chips including one on a chip level and the other on a wafer level, and a chip-to-chip stacking method that bonds together the mutually corresponding chips each on a chip level.
Claims7
A method for fabricating a semiconductor device having a three-dimensional integrated circuit formed by stacking at least three or more plurality of chips, comprising the step of:
- stacking the plurality of chips using at least two or more of three stacking methods which are a wafer-to-wafer stacking method that bonds together the mutually corresponding chips each on a wafer level, a chip-to-wafer stacking method that bonds together the mutually corresponding chips including one on a chip level and the other on a wafer level, and a chip-to-chip stacking method that bonds together the mutually corresponding chips each on a chip level.
A method for fabricating a semiconductor device, comprising the steps of:
- (a) stacking a plurality of first wafers each provided with a plurality of memory chips so as to electrically connect the mutually corresponding memory chips to each other with first through-silicon-vias to form a wafer stack;
- (b) dividing the wafer stack by dicing to form a plurality of first chip-to-chip stacks;
- (c) stacking the plurality of first chip-to-chip stacks and a second wafer provided with a plurality of interface chips so as to electrically connect the first chip-to-chip stacks and the interface chips, which correspond to each other, with second through-silicon-vias to form a first chip-to-wafer stack;
- (d) dividing the first chip-to-wafer stack by dicing to form a plurality of second chip-to-chip stacks;
- (e) stacking the plurality of second chip-to-chip stacks and a third wafer provided with a plurality of logic chips so as to electrically connect the second chip-to-chip stacks and the logic chips, which correspond to each other, via third through-silicon-vias to form a second chip-to-wafer stack;
- and
- (f) dividing the second chip-to-wafer stack by dicing to form a plurality of third chip-to-chip stacks.
Dependencies are inferred from the claim text.