Semiconductor device and manufacturing method thereof
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorShunpei YAMAZAKI
Life of this patent
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Abstract
An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.
Claims21
A method for manufacturing a semiconductor device, comprising:
- forming a first conductive layer over a substrate;
- selectively forming a resist mask with plural thicknesses over the first conductive layer;
- etching the first conductive layer by using the resist mask to form a gate electrode and a first wiring;
- removing the resist mask over the gate electrode and leaving part of the resist mask over the first wiring;
- forming a gate insulating layer so as to cover the gate electrode, the first wiring, and the resist mask;
- forming a second conductive layer over the gate insulating layer;
- selectively etching the second conductive layer to form a source and drain electrodes, and to form a second wiring overlapping the first wiring;
- and
- forming a semiconductor layer in contact with the source and drain electrodes in a region overlapped with the gate electrode.
A method for manufacturing a semiconductor device, comprising:
- forming a first conductive layer over a substrate;
- selectively forming a resist mask over the first conductive layer;
- etching the first conductive layer by using the resist mask to form a gate electrode and a first wiring;
- removing the resist mask over the gate electrode and the first wiring;
- forming an insulating layer over the first wiring;
- forming a gate insulating layer so as to cover the gate electrode, the first wiring, and the insulating layer;
- forming a second conductive layer over the gate insulating layer;
- selectively etching the second conductive layer to form a source and drain electrodes, and to form a second wiring overlapping the first wiring;
- and
- forming a semiconductor layer in contact with the source and drain electrodes in a region overlapped with the gate electrode.
A method for manufacturing a semiconductor device, comprising:
- forming a first conductive layer over a substrate;
- selectively forming a resist mask over the first conductive layer;
- etching the first conductive layer by using the resist mask to form a gate electrode and a first wiring;
- removing the resist mask over the gate electrode and the first wiring;
- forming a gate insulating layer so as to cover the gate electrode and the first wiring;
- forming an insulating layer over the gate insulating layer;
- forming a second conductive layer over the insulating layer;
- forming a first semiconductor layer over the second conductive layer;
- selectively etching the first semiconductor layer, the second conductive layer and the insulating layer to form a source and drain electrodes, and to form a second wiring overlapping the first wiring;
- and
- forming a second semiconductor layer in contact with the source and drain electrodes in a region overlapped with the gate electrode.
Dependencies are inferred from the claim text.