Passive device trimming

A method for improving process control of one or more capacitors formed on a semiconductor body, comprising:

• forming an upper capacitor electrode layer comprised within the one or more capacitors on the semiconductor body;
• measuring an operational parameter of respective capacitors;
• forming an adjustment map illustrating variations in the operational parameter of respective capacitors as a function of a spatial location on the semiconductor body;
• and
• selectively patterning an etch mask layer based upon the adjustment map using a reticleless exposure system;
• and
• selectively trimming the upper capacitor electrode layer of the one or more capacitors in-situ to processing the semiconductor body, wherein selectively trimming the upper capacitor electrode layer comprises etching the selectively patterned etch mask layer to reduce the size of the underlying upper capacitor electrode layer in regions exposed by the etch mask layer.

A method for improving process control of one or more resistors formed on a semiconductor body, comprising:

• forming the one or more resistors on the semiconductor body, wherein respective resistors comprise:
• a first resistor head;
• a second resistor head;
• a resistor body;
• measuring a sheet resistance of respective resistors;
• forming an adjustment map illustrating variations in the sheet resistance of respective resistors as a function of a spatial location on the semiconductor body;
• and
• selectively patterning an etch mask layer based upon the adjustment map using a reticleless exposure system;
• and
• selectively trimming the one or more resistors in-situ to processing the semiconductor body, wherein selectively trimming the one or more resistors comprises etching the selectively patterned etch mask layer to trim the underlying resistive layer in regions exposed by the etch mask layer.