Discrete fourier transform processing apparatus and radio communication apparatus
AssigneeFujitsu Limited
InventorJun KAMEYA
Life of this patent
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Abstract
An arithmetic processing apparatus includes a shift section configured to shift, by (N+1)/2 bit data, a data signal x(n) (n=0, . . . , N−1), which has a data length of N, where N is an odd number, and which has left-right symmetry with respect to ((N−1)/2)th bit data, so as to obtain a data signal x′(n), and an arithmetic operation section configured to obtain a data signal X(k) (k=0, . . . , N−1) by performing a discrete Fourier transform operation on the data signal x′(n).
Claims9
An arithmetic processing apparatus comprising:
- a shift section configured to shift, by (N+1)/2 bit data, a data signal x(n) (n=0, . . . , N−1), which has a data length of N, where N is an odd number, and which has left-right symmetry with respect to ((N−1)/2)th bit data, so as to obtain a data signal x′(n);
- and
- an arithmetic operation section configured to obtain a data signal X(k) (k=0, . . . , N−1) by performing a discrete Fourier transform operation on the data signal x′(n).
A radio communication apparatus configured to transmit a random access channel by using a data signal x(n) (n=0, . . . , n−1) which has a data length of N bits, where N is an odd number, and which has left-right symmetry with respect to ((N−1)/2)th bit data, the radio communication apparatus comprising:
- a shift section configured to shift the data signal x(n) by (N+1)/2 bits, so as to obtain a data signal x′(n);
- a discrete Fourier transform operation section configured to obtain a data signal X(k) (k=0, . . . , N−1) by performing a discrete Fourier transform operation on the data signal x′(n);
- and
- a phase rotation operation section configured to perform an operation to rotate a phase of the data signal X(k).
Dependencies are inferred from the claim text.