Internal write/read pulse generating circuit of a semiconductor memory apparatus
AssigneeHynix Semiconductor Inc.
InventorSANG HEE LEE
Life of this patent
Estimating the term…
Abstract
A control clock generating unit outputs a clock as a control clock when a column address strobe pulse is input and fixes the control clock to a specific level when an all bank precharge signal or a refresh signal is enabled. An internal pulse generating unit outputs an external write pulse or an external read pulse as an internal write pulse or an internal read pulse in response to the control clock.
Claims9
An internal write/read pulse generating circuit of a semiconductor memory apparatus comprising:
- a control clock generating unit configured to output a clock as a control clock when a column address strobe pulse is input and fix the control clock to a specific level when an all bank precharge signal or a refresh signal is enabled;
- and
- an internal pulse generating unit configured to output an external write pulse or an external read pulse as an internal write pulse or an internal read pulse in response to the control clock.
An internal write/read pulse generating circuit of a semiconductor memory apparatus configured to output an external write pulse as an internal write pulse after a predetermined number of clock periods of a clock or an external read pulse as an internal read pulse when the external write pulse or the external read pulse is input, wherein when a column address strobe pulse is input, transistors responding to the clock among transistors comprising the internal write/read pulse generating circuit repeat a turn on or turn off operation according to the clock and when an all bank precharge signal or a refresh signal is enabled, the transistors responding to the clock are fixed to either of the turn on or turn off state.
Dependencies are inferred from the claim text.