Dynamic random access memory with shadow writes

A method for improved access to a dynamic random access memory (DRAM), the method comprising:

• latching a valid write column address strobe (CAS) address for accessing the DRAM in response to receiving an external write CAS signal;
• buffering a set of write data values to be stored in a first set of DRAM locations corresponding to the write CAS address;
• issuing an internal read CAS signal in response to receiving an external read CAS signal to indicate a valid read CAS address, and concurrent with buffering the set of write data values;
• issuing an internal write CAS signal after issuing the internal read CAS signal and after buffering the complete set of write data values;
• and
• reading a set of read data values from a second set of DRAM locations corresponding to the read CAS address, after issuing the internal write CAS signal.

A memory controller comprising:

• a shadow control logic to issue a write column address strobe (CAS) to a dynamic random access memory DRAM to latch a valid write CAS address for accessing the DRAM;
• a write queue to assert a set of write data values to be stored in a first set of DRAM locations corresponding to the write CAS address;
• said shadow control logic to issue a read CAS to the DRAM to indicate a valid read CAS address, after asserting the write CAS and prior to said asserting of the set of write data values is complete;
• and
• a read queue to receive a set of read data values from a second set of DRAM locations corresponding to the read CAS address, after asserting the complete set of write data values.

A dynamic random access memory (DRAM) module comprising:

• a plurality of DRAM locations to store data, said plurality of DRAM locations being organized into banks of DRAM locations and the banks of DRAM locations being further organized into bank groups;
• a shadow control logic to receive an external write column address strobe (CAS) signal to indicate a valid write CAS address and to subsequently receive an external read CAS signal to indicate a valid read CAS address;
• an address latch responsive to the shadow control logic, after receiving the external write CAS signal, to latch the valid write CAS address for accessing the DRAM;
• a data buffer, responsive to the shadow control logic, to buffer a set of write data values to be stored in a first set of DRAM locations corresponding to the write CAS address;
• said shadow control logic to issue an internal read CAS signal in response to receiving the external read CAS signal, and concurrent with said buffering of the set of write data values, and to issue an internal write CAS signal after issuing the internal read CAS signal and after the buffering of the set of write data values is complete;
• and
• a column decoder to decode the read CAS address to read a set of read data values from a second set of DRAM locations, after issuing the internal write CAS signal.

A computing system comprising:

• an addressable memory including a dynamic random access memory (DRAM) module;
• a processor operatively coupled with the addressable memory to issue write requests and read requests corresponding to storage locations in the addressable memory;
• a memory controller coupled with the addressable memory and including a first shadow control logic, the first shadow control logic being responsive to receiving a processor write request to the addressable memory to:
• issue an external write column address strobe (CAS) to the DRAM module to latch a valid write CAS address for accessing the DRAM,
• assert a set of write data values to be stored in a first set of DRAM locations corresponding to the write CAS address;
• the first shadow control logic of said memory controller further being responsive to receiving a processor read request from the addressable memory to:
• issue an external read CAS to the DRAM module to indicate a valid read CAS address, after asserting the external write CAS and prior to asserting the complete set of write data values, and
• receiving a set of read data values from a second set of DRAM locations corresponding to the read CAS address, after asserting the complete set of write data values.