Row decoder for a memory device

A method for managing a memory device, including:

• storing data into an array of memory cells arranged in a plurality of rows and a plurality of columns, the rows of the array being associated respectively with word lines identified by respective row addresses, wherein the step of storing data includes:
• receiving a current row address;
• selecting a word line according to said current row address, wherein said selecting the word line includes:
• providing the current row address to a set of row selection units associated respectively with the word lines;
• and
• enabling a selected row selection unit, of the set of row selection units, associated with a selected word line, of the word lines, corresponding to the current row address after a time from receiving the current row address for biasing the selected word line to a selection voltage.

An electronic system, comprising:

• a processor;
• input/output units for receiving and providing data;
• and
• a memory that includes:
• an array of memory cells arranged in a plurality of rows and in a plurality of columns;
• a plurality of word lines associated respectively with the rows of the array and identified by respective row addresses;
• a row decoder configured to receive a current row address and select a selected word line of the word lines according to said current row address, the row decoder including:
• a plurality of row selection units associated respectively with the word lines and configured to receive the current row address, each row selection unit being configured to be enabled for biasing the respective word line to a selection voltage if the current row address identifies said word line, wherein:
• each row selection unit includes a corresponding enabling device for enabling the row selection unit after a time from the reception of the current row address.