US 2010/0165771 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device comprises a plurality of word lines, a plurality of bit lines intersecting the word lines, a memory cell array having a plurality of memory cell each provided at an intersection of the word line and the bit line, a plurality of sense amplifier each of which detects and amplifies a signal level of the bit line, a replica word line, a replica bit line intersecting the replica word line, a replica memory cell provided at each intersection of the replica word line and the replica bit line, a replica circuit which simulates reading out of the memory cell, and a timing generating circuit which quantizes a replica delay time that is a time until the replica bit line changes from a reference timing, and which generates an activation timing for the sense amplifier based on a quantization result.

Claims20

Dependent claims

A semiconductor memory device comprising:

a memory cell array comprising a plurality of word lines, a plurality of bit lines across the plurality of word lines, and a plurality of memory cells at intersections of the word lines and the bit lines;
a plurality of sense amplifiers configured to detect signal levels of the bit lines and to amplify the signal levels of the bit lines;
a replica circuit comprising a replica word line, a replica bit line intersecting the replica word line, and a replica memory cell at an intersection of the replica word line and the replica bit line, the replica circuit being configured to simulate a read-out operation of the memory cell;
and
a timing generator configured to quantize a replica delay time from a reference time to when a signal level of the replica bit line changes, and to generate an activation time for the sense amplifier based on a quantization result.

2 more elements

A semiconductor memory device comprising:

a memory cell array comprising a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of memory cells at intersections of the word lines and the bit lines;
a plurality of sense amplifiers configured to detect signal levels of the bit lines and to amplify the signal levels of the bit lines;
a replica bit line comprising a same configuration as the bit line, and configured to simulate a change in a signal of the bit line;
and
a timing generator configured to quantize a replica delay time from a reference time when the word line is selected to a time when a signal level of the replica bit line changes, and to generate an activation time for the sense amplifier based on a quantization result.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20